Hardware-Native Hyperdimensional Computing for Lower-Limb EMG Classification on a Resource-Constrained GateMate FPGA

Abstract

Electromyography (EMG)-controlled orthoses and wearable assistive systems require classifiers that combine accurate motion recognition, efficient embedded deployment, and support for local model formation. Long-term EMG deployment is affected by signal drift and inter-session variability, motivating architectures that can support post-deployment model updates. Local processing can reduce dependence on external computation and data transfer. To address these challenges, this work presents a hardware-targeted Hyperdimensional Computing (HDC) classifier for trainable EMG classification on the resource-constrained GateMate A1 FPGA from Cologne Chip. The proposed architecture performs on-device HDC model formation and inference directly on FPGA. Linear Discriminant Analysis (LDA) serves as a conventional offline-trained and FPGA-inferred baseline. The evaluation uses eight anonymized single-session EMG recordings from seven healthy participants and one participant with spinal cord injury with 32 channels and five motion classes and includes accuracy, robustness, and routed FPGA implementation analysis. Across all recordings, the per-recording best-case HDC configurations reach 95.20% classification accuracy, while the LDA baseline achieves 98.54% overall accuracy. Under controlled input perturbation with a standard deviation of σ=0.10, HDC retains 92.98% mean accuracy compared with 80.98% for LDA. A first board-level power measurement indicates an energy cost of approximately 0.40 mJ per inference sample and 0.87 mJ per training sample. The experiments demonstrate single-session on-device HDC model formation and inference, while longitudinal validation, fatigue robustness, electrode-shift robustness, and inter-session adaptation remain future work. The results indicate that HDC provides an architectural foundation for trainable wearable edge–AI systems with local model updates.