Programmable Data Planes for AI Infrastructure Readiness: Abstractions, Accelerators, and Systems—A Survey

Abstract

Software-Defined Networking (SDN) enables data plane programmability and allows for customised, high-speed packet processing that transcends the limitations of fixed-function hardware. This flexibility is increasingly vital for modern networks tasked with supporting intensive workloads, such as distributed AI training and real-time telemetry. However, supporting these workloads in practice is far from straightforward, as each technology operates within strict physical and architectural boundaries that ultimately determine what is feasible at deployment. This survey provides a detailed examination of the practical capability boundaries of prominent programmable data plane technologies, including Protocol-Oblivious Forwarding (POF), Programming Protocol-independent Packet Processors (P4), the extended Berkeley Packet Filter (eBPF), and the Network Programming Language (NPL). It traces their evolution and functional capabilities. We further explore the prevailing system designs and hardware platforms, spanning Application-Specific Integrated Circuits (ASICs) switches, Smart Network Interface Cards (SmartNICs) or Data Processing Units (DPUs), Field-Programmable Gate Arrays (FPGAs), and kernel or eXpress Data Path (XDP)-based software targets. A central concern of this survey is bridging the gap between theoretical programmability and what these platforms can realistically deliver in production. To that end, we map each hardware profile to concrete deployment scenarios, examining how these data planes are currently used across cloud data centres, edge and telco networks (including 5G and emerging 6G), and distributed AI and High-Performance Computing (HPC) clusters. Finally, we explore emerging high-speed communication fabrics and AI compute-enabled data planes, outlining the open challenges that will shape the next generation of intelligent networked systems.