Design and Implementation of a Custom Multiply Accumulate Instruction in an Open-Source RISC-V Processor Core

Abstract

With the rise in popularity of applications requiring high-performance arithmetic acceleration, there’s an increasing need for architectural enhancements to low-power embedded and signal processor cores. This paper discusses the design and hardware implementation of an application-specific Multiply-Accumulate (MAC) instruction developed for the open-source PicoRV32 RISC-V processor using the Pico Co-Processor Interface (PCPI). A new opcode-based decode mechanism will enable this process, where a specific field will be checked in the instruction to activate the MAC operation, without having to change the underlying RISC-V ISA. Register-to-register execution will be possible in this hardware MAC-based architecture because it will allow for two-operand forwarding from the processor register file to the hardware MAC unit and back through the PCPI for write-back. The design has been implemented in Verilog and verified through functional simulation and FPGA synthesis by using Vivado. Synthesis results indicate that the MAC-enabled processor utilizes an area-efficient design, where 1,338 LUTs, 953 flip-flops, 2 DSP slices, and very little BRAM were used. Performance metrics show that significant reductions in execution cycles were achieved from the MAC-enabled processor versus a baseline RISC-V processor and therefore validates the efficacy of the proposed custom instruction for compute-intensive workloads