TL;DR
It is demonstrated that defining the learning target according to the error structure and decomposing the calibration responsibility can effectively improve the dynamic performance of pipelined ADCs while retaining substantial calibration gains under limited training-condition coverage.
Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) are significantly impacted by capacitor mismatch during the quantization of analog signals, which severely affects ADC accuracy. This paper builds upon code density calibration based on the binary algorithm to calibrate a non-binary redundant SAR...
This work presents a dynamic comparator calibration architecture that works entirely in the digital domain with no analog correction element of any kind. The system is built around a StrongARM latch comparator paired with a 7-bit on-chip timeto-digital converter (TDC). Since comparator offset shifts the switching insta...
A digital calibration method with reduced LUT complexity is presented to suppress code-domain nonlinear errors caused by CDAC mismatch in high-resolution SAR ADCs. The method exploits the MSB-dominant and locally correlated behavior of mismatchinduced errors, so that interval-wise error estimation and correction can be...
This paper presents an observer–data-path decoupled time-domain ADC with three-stage digital background calibration, designed and comprehensively verified through post-layout simulations in 28 nm CMOS for highly integrated micro-systems. In scaled nodes, the voltage-to-time converter front-end exhibits large-signal non...
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