Formal Verification of Hardware-Software Co-Design using Temporal Logic

Abstract

This paper presents a novel approach to formally verifying hardware-software co-design using temporal logic. Traditional verification methods often struggle to account for the intricate, time-dependent interactions inherent in these systems. We propose a methodology centered around constructing a formal model of the co-design system utilizing temporal logic, enabling the automated generation of test cases and verification of system properties across time, incorporating timing constraints and inter-domain communication. The core contribution lies in providing a rigorous framework for ensuring correctness within the dynamic complexities of hardware-software co-design. The approach aims to mitigate the risks associated with complex designs by offering a quantifiable and verifiable solution. This work explores the feasibility and potential of temporal logic as a robust tool for ensuring the reliability and functional correctness of modern hardware-software systems.