Jul 2026· IEEE International Conference on Consumer Electronics· pp. 155-160· 0 citations· 16 references
Abstract
This work proposes a conceptual Single-Pixel Camera (SPC) architecture that integrates Dynamic Resolution Imaging (DRI) with an FPGA-based Orthogonal Matching Pursuit (OMP) reconstruction engine. The proposed OMP-DRI accelerator supports progressive multi-resolution reconstruction with measurement reuse, enabling early low-resolution preview and subsequent refinement. The design is developed using High-Level Synthesis (HLS), translated into RTL, and verified on a Zynq UltraScale+ FPGA platform using MATLAB-generated sensing matrices and measurement vectors transferred through DDR and DMA. The accelerator employs correlation-based atom selection, QR/MGS refinement, ISR-assisted normalization, residual update, and division-free back-substitution with 18-bit fixed-point arithmetic. Compared with the MATLAB floating-point reference, the selected format achieves an NMSE of approximately $2.77 \times 10^{-7}$ for measurement values ranging from 0 to 1023. The current implementation supports 4 $\times$ 4, 8 $\times$ 8, and 16 $\times$ 16 resolution levels, with reconstruction latencies of 75.2 $\mu \mathbf{s}$, 125.73 $\mu \mathbf{s}$, and 555.77 $\mu \mathrm{~s}$ at 138 MHz. These results demonstrate the feasibility of an embedded FPGA-based OMP-DRI reconstruction accelerator within the proposed SPC framework, while complete optical SPC integration remains future work.
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