R. Ratnakumar

A Modulo-11 and DMR-based Fault-Tolerant Signed Baugh–Wooley Multiplier with 100% Single-Bit Fault Detection

Congestion-Aware Physical Synthesis and RTL-to-GDSII Implementation of a 90nm RISC-V Execute Pipeline Stage using Cadence Genus and Innovus

This manuscript presents a congestion-aware RTL-to-GDS-II physical synthesis of a RISC-V Execute (EX) pipeline stage at the 90 nm CMOS technology node using Cadence tools- Genus and Innovus. The EX stage integrates a 32-bit ALU, forwarding unit, branch comparator, barrel shifter, operand multiplexers, and EX/MEM pipeli...

High Performance Fault-Resilient MAC Architecture for Mission-Critical AI Hardware

Multiply Accumulate (MAC) units play an important role in high-performance AI/ML and digital signal processing systems where both reliability and computational efficiency are critical for achieving optimal performance. In this work, an optimized MAC unit is designed and implemented by integrating a Wallace Tree Multipl...