Conference

A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications

P. Nagabushanam N. Umasree Radha Subramanyam V. K. P. Kiranmaie P. V. Kumar

Aug 2026 · International Conference Electronic Systems, Signal Processing and Computing Technologies [ICESC-] · pp. 841-846 · 0 citations · 3 references

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