Energy-Efficient Approximate Multipliers Based on Error-Compensating Approximate Adders

Abstract

This work presents energy-efficient approximate multipliers based on two complementary types of approximate adders, one that underestimates and another that overestimates the result of addition. Owing to their simplified logic structures, these adders significantly reduce hardware cost. The main strength of the proposed approach lies in exploiting the complementary error behavior of these adders. When strategically placed within the partial product reduction stage of an approximate multiplier, their opposing error tendencies enable effective error compensation, resulting in a favorable balance between accuracy and hardware efficiency. Applying these adders to 8–11 least significant columns of an 8-bit multiplier yields substantial hardware improvements, including up to 53% reduction in delay, 82% reduction in energy consumption, and 76% reduction in area, while maintaining mean relative error distance (MRED) values between 3.4% and 12.1%. For similar accuracy levels, the proposed multipliers consistently outperform state-of-the-art approximate multipliers in terms of delay, power, and area. The architecture is scalable, allowing larger bit-width multipliers to be constructed iteratively from smaller configurations, with increasing hardware benefits observed at higher bit-widths for comparable normalized error levels. This work further evaluates the proposed multipliers in practical applications, including deep neural networks and image processing. When integrated into the fine-tuned ViT-Small vision transformer model, the design incurs only a 0.1% reduction in classification accuracy while achieving 37% energy and 40% area savings compared to an exact multiplier. Image multiplication and Sobel edge detection experiments also demonstrate high output quality, with PSNR and SSIM values exceeding 30 dB and 0.9, respectively.