Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Packets are Not Pages: Flow-Based Addressing Conserves Memory Bandwidth

SmartNICs promise hardware offloading for network applications like traffic analysis and virtual host dispatching. However, due to memory bandwidth limitations, SmartNICs are unable to effectively accelerate applications like intrusion detection and deep packet inspection that require high-speed reassembly. We argue that this limitation is due to an architectural mismatch: variable-sized packets arrive out of order, but a SmartNIC's memory is a contiguous address space broken up into fixed-size pages. This mismatch forces multiple unnecessary copies to translate between the two layouts. We propose a new memory addressing scheme, flow-based addressing, which enables software to access the reassembled payloads of a flow's packets as a contiguous region in memory. Flow-based addressing allows software to easily operate on reassembled payloads without copies, dramatically reducing memory traffic. Eliminating copies entirely requires hardware that maps logical flow offsets to non-contiguous physical addresses and assembles misaligned payloads into contiguous cache lines at line rate. The new memory addressing scheme introduces three architectural mechanisms: a flow translation table, a private flow cache, and a specialized DMA engine that assembles unaligned, variable-length packets into contiguous cache lines. We describe a prototype design on an FPGA-based SmartNIC and show that, across synthetic microbenchmarks, university campus network traffic, and data center web-search traffic, flow-based addressing reduces DRAM bandwidth use by 77-83%, lowers execution time by 25-62%, and increases per-core throughput by 1.33-2.66×.

HostPIMSim: A High-Productivity Framework for Host-Side Processing-in-Memory Simulation

MEMPOWER: Efficient Power Management with Fine-grained Memory Analysis and Modeling for HPC Workloads

MEPOWER is proposed, a flexible, model-based approach to exposing compute/data movement imbalance that characterizes the fine-grained memory behavior of parallel workloads that demonstrates a reduction in EDP on a range of HPC benchmarks with minimal impact on execution time when compared to the standard OS/hardware-managed power control mechanism.

Lost Bytes At The Crossroads Between User-And Kernel-Level Memory Management

With soaring DRAM prices, optimizing software for efficient memory use is becoming increasingly important. Essential to this end is the memory management component of the software's language runtime. This component requests page-sized memory from the kernel and subdivides it into smaller blocks to satisfy allocations performed by the software. Since DRAM was comparatively cheap for the preceding decade, contemporary prior work has focused on optimizing this component for performance. A key optimization is conducted on the free path where memory freed by the software is not directly returned to the kernel to satisfy future allocations and avoid costly context switches. In this work-in-progress paper, we illustrate the lost potential of user-level allocators for system-wide memory use. We show that—since the kernel manages memory at page-granularity—the user-level allocation scheme must be designed with page alignment in mind. We provide a classification for physical memory that is lost due to the mismatch of user-space and kernel-space allocation granularities. To empirically illustrate the potential of such an allocation scheme, we conduct experiments with the mallocng allocator where we identify potential savings of up to 75 percent.

VCSRT extended page table assisted virtual memory mapping framework for efficient dynamic resource allocation in industrial edge virtualized runtimes

The shift toward the Industrial Internet imposes new requirements on industrial edge runtime systems for rapid resource configuration and dynamic application deployment. However, existing embedded and real-time runtimes suffer from low efficiency and redundant logic in dynamic physical memory management, which can hardly meet the deterministic demands of industrial mixed-criticality scenarios. To address these limitations, this paper proposes VCSRT, a hardware-assisted virtual memory mapping framework tailored for industrial edge scenarios. It integrates three core components: an optimized Lazy Buddy system for on-demand memory allocation, Extended Page Table (EPT)-based hardware-accelerated address translation, and priority-aware scheduling adapted to industrial workloads. By eliminating the architectural redundancy of conventional virtual memory stacks, VCSRT substantially improves memory allocation efficiency and deterministic resource provisioning. Experimental results validate that VCSRT achieves substantial reductions in worst-case allocation latency and worst-case execution time of high-priority tasks under heavy load, and maintains microsecond-level response jitter stability across all load levels. The proposed framework can provide efficient and deterministic memory resource support for industrial edge dynamic reconfiguration applications.

Memory Allocation for Constant-Bounded Programs

This work studies memory allocation for constant-bounded programs, whose execution length is syntactically limited for all inputs. Examples of such programs include verified kernel extensions, cryptographic routines, and fixed-shape machine-learning models. We show that constant boundedness enables a tight, polynomial-time approximation of optimal stack usage by viewing control flow as a tree and applying a tree-scan allocation strategy augmented with memory defragmentation. Our approach guarantees memory usage bounded by the maximum live memory plus, at most, the size of the largest buffer, and is optimal when in-place swapping is permitted. We deploy the proposed allocator in two scenarios. First, in an Elixir-to-eBPF compiler, as a spiller that optimizes stack space. Second, as a static heap allocator for bounded MLIR programs using the Structured Control-Flow dialect. Results demonstrate stack reductions exceeding 90% on real eBPF workloads and show that, even under aggressive code expansion, defragmentation is rarely required and memory usage remains a small fraction of that required by naive allocation strategies.