A Low-Power Pipelined IEEE 754 Floating-Point Datapath for Energy-Efficient Neural Network Acceleration

Abstract

The fast advancement of deep neural networks has led to the escalation of hardware accelerator needs that achieve high functionality as they comply with strict requirements of power and latency, particularly in edge and embedded artificial intelligence. In this paper, the research introduce a low power, pipelined single-precision (32 bits) floating-point data path that is to be used in neural network accelerators compliant with the IEEE 754 single-precision standard. The suggested design uses multi-stage pipelining on addition, multiplication and accumulation units, which greatly decreases the critical path delays and enhances the overall throughput. Efficiency of power is also by ensuring that its techniques such as operand isolation, clock-conscious staging of pipelines and minimized switching activity in arithmetic units. The architecture has a combined optimization in latency, energy, and numerical accuracy, making it possible to infer the numerical accuracy of resource-constrained platforms in real-time. Simulations after synthesis show that the proposed data path has significant propagation delay and dynamic power improvements over the state-of-the-art non-pipelined floating-point implementations and can compute the accuracy needed by the deep learning workloads. Its scalable and modular design is flexible and can be easily adapted to other neural network designs. The findings demonstrate the strength of the targeted design towards addressing the increasing demand of high-performance, low-energy neural network hardware, which provides a viable approach to edge AI systems with severe demands on both power and performance.