Hybrid RRAM-SRAM Computing-in-Memory Architecture Enabling Inference and Fine-Tuning

Abstract

Benefiting from high energy efficiency and massive computing parallelism, computing-in-memory (CIM) has emerged as one of the most promising paradigms for implementing neural networks. However, traditional CIM architectures are primarily designed for inference only. Several prior works enable neural network fine-tuning, but they still rely on frequent data interaction with off-chip DRAM. In this paper, the hybrid RRAM-SRAM CIM architecture that enables inference and finetuning is proposed. The inference layers are mapped onto highdensity RRAM CIM arrays to fully exploit parallel computation, while the fine-tuning layers are deployed on SRAM CIM arrays to support frequent weight update and backward propagation. Furthermore, a 14T digital SRAM CIM cell is designed that supports both forward inference and backward propagation. Based on the NeuroSim platform, system-level evaluations of the above innovations are conducted. Experimental results demonstrate that the proposed hybrid architecture achieves the higher peak energy efficiency of 20.76 TOPS/W, outperforming the state-of-the-art by 2.30×.