Design of Low-Delay Approximate Multiplier Using 4–2 Compressor with EDC

Abstract

Recently, approximate computing has become an active topic of interest as a state of the art method to enhance the efficiency in both performance and energy consumption of the arithmetic circuits in error-tolerant applications. Numerous multimedia, image processing, and machine learning systems today can accept some small errors in computation in order to have simpler hardware and run more quickly. This paper presents a probability-conscious low- delay approximate multiplier design with an Error Detection and Correction (EDC) improved 4-2 compressor in order to attain a favorable tradeoff between accuracy, performance, and power. The proposed design presents an approximation approach based on probability when completely reducing the products, selecting to approximate non-critical calculation routes and maintaining accuracy in the high-impact ones. The structure of the compressor is optimized into a 4-2 compressor to speed up the reduction phase and reduce the propagation delay. To enhance the reliability further, an EDC module is incorporated to identify and address the major approximation errors thereby restraining the spread of errors in the multiplier. The 16-bit multiplier architecture comes in two variants that are implemented and synthesized using standard hardware design tools to test the performance in terms of delay, power, and area. According to experimental evidence, both power consumption and propagation delay have been significantly reduced relative to conventional implementations of exact multipliers and the computational accuracy is acceptable. Image processing based application level validation proves that the proposed architecture maintains the quality of the output and gives better hardware efficiency.