Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing

Robust Hybrid Computing-in-Memory System Based on 2T-2C and 4T-2C FRAM Cells

This paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array that provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption.

FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

Flexibility and customization make Field-Programmable Gate Arrays (FPGAs) attractive for arbitrary-precision arithmetic-heavy workloads such as sparse and mixed-precision DNN inference. However, in modern logic blocks, the hardware adder chain is typically driven only by look-up table (LUT) outputs, preventing adders a...

Design of a 1-bit Adder/Subtractor Using Multi-Gate Transistors for High Speed and Low Power Applications

Compact and energy-efficient adder and subtractor circuits are the basic building blocks of the arithmetic circuits. This work presents the conceptual design of a 1-bit adder/subtractor using four Functionally Programable Logic cells (FPLCs). Each FPLC is realized using non aligned multi-gate field-effect transistors (...

Adaptive Precision Hierarchical Vedic Multiplier with CSA-Based 64-Bit Optimization for Low-Power FPGA Applications

In this paper, an energy-efficient Vedic multiplier design is presented through runtime-adaptive hierarchy. In the proposed architecture, the Urdhva-Tiryakbhyam Vedic algorithm has been implemented recursively from 2x2 to 32$\times$32 bit multiplication in a modular hierarchical fashion. In addition, the multiplier has...

A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications

Design Space Exploration of In-Memory Computing Implementations for Discrete Fourier Transform

Although memristor-based in-memory computing (IMC) has been widely investigated for brain-inspired neuromorphic workloads, systematic evaluations of its energy, latency, and signal-to-noise ratio (SNR) trade-offs across diverse system parameters remain scarce for classical digital signal processing (DSP). To address th...