Robust Hybrid Computing-in-Memory System Based on 2T-2C and 4T-2C FRAM Cells
TL;DR
This paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array that provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption.
Abstract
The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges, this paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array. The proposed architecture performs majority-based bitwise computation by simultaneously activating multiple word lines, enabling AND and OR operations in conventional 2T-2C FRAM cells. Selectively embedded 4T-2C FRAM cells further provide in-array inversion, extending the supported functions to NOT and functionally complete Boolean logic. The architecture also supports full-adder operations and stores input operands, intermediate data, and output results within the same FRAM subarray, thereby reducing data movement. Moreover, the architecture provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption. The internal computation, nevertheless, relies on analog charge sharing and differential sense-amplifier resolution. HSPICE simulations indicate PVT-evaluated sensing stability and computational efficiency under the evaluated conditions. The bit-line voltage difference reaches 337 mV under triple-row activation and 214 mV under quintuple-row activation, with the former being 5.2 times that of the reported DRAM implementation used for comparison. At 3.3 V, process–voltage–temperature (PVT) simulations show that the maximum deviation of ΔV from its mean value remains below 4.62% across the evaluated process corners and temperatures from −40 °C to 125 °C. Simulations of the 8 × 8 FRAM CiM compute-array circuit model yield an energy consumption of 1.94–3.46 pJ/bit and a calculation latency of 0.599–1.167 ns for the supported bitwise operations, corresponding to a 4.86×–5.90× reduction in energy consumption compared with the reported DDR3-based design. The architecture also supports parallel processing and mitigates data loss associated with destructive FRAM readout through an in-array replication mechanism. Finally, an 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed hybrid architecture, and its basic array functionality was verified.