Adaptive Approximate Multiplier using Error Tolerant Adders for Low Power Applications
TL;DR
The obtained results demonstrate that the proposed architecture offers improved computational efficiency while maintaining acceptable numerical accuracy, making it suitable for low-power and high-performance approximate computing applications.
Abstract
The approximate computing has gained popularity in recent years due to effective usage of bandwidth with good data rate. This paper focuses on development of unified multiplier using various approximate adders like LOA, HERLOA, ETAI and PAAA. Also, the error analysis is performed by using the parameters like MED, ER, NMED, worst-case error and best-case error. Among the four modes, Mode 3 (PFAA) achieved the best overall error performance, outperforming the remaining modes in both quantitative and qualitative analysis. Also, Mode 3 provides up to 21.55% reduction in MED, 16.67% reduction in worst-case error, and improved error resilience with the state of art approximate multiplier designs but trades off in setup and hold time delay. The obtained results demonstrate that the proposed architecture offers improved computational efficiency while maintaining acceptable numerical accuracy, making it suitable for low-power and high-performance approximate computing applications.